A test processor can be used in smart test of an IC (Integrated Circuit) such as a memory or SoC (System on Chip) IC. However, usually there is no register unit or calculation unit in the test processor and so conditional execution cannot be performed. The test processor typically can only execute a nested repeat tree like the following:
repeat 10{100 vectorsrepeat 5{1024 vectors}30 vectors}
wherein “repeat” represents an act of repeating, for example, “repeat 10” representing repeating 10 times the content in the parentheses thereafter; and “vector” represents a data vector. By executing the repeat tree, the test processor can generate the binary sequence for the test. The test processor includes, for example, a repeat tree execution module that converts the repeat tree into a binary sequence, and an excitation signal generation module that generates an excitation signal to be input into a test device based on the binary sequence.
An MTL (Memory Test Language) compiler is typically used to convert a test program written in a test language into a repeat tree. Because an MTL compiler can generate a repeat tree for each pin, it is also commonly referred to as a per-pin algorithmic pattern generator (APG).
The test language could be C language or any other suitable language. C language and other language similar to C language will be referred to as C-style language hereinafter, and an illustration will be made by example of C-style language. In this case, the MTL compiler converts C-style programming patterns (a C-style program) into repeat trees for respective pins, an example of which is as follows:
wherein “dev_acc” references to a device access timing generation module in the MTL compiler, “apgAccess” is an instance of the device access timing generation module, and “pin 0: repeat 512 {HL}” and “pin1: repeat 256{0011}” on the right side represent repeats (or repeat trees in complex cases) executed for pin No. 0 and pin No. 1, respectively, which are also called device access lines. In this manner, the above test program is converted into repeat trees for respective pins.
An MTL compiler typically includes a semantic processor and one or more device access timing generation modules. The semantic processor can interpret the programming patterns (program sentences) of a test program. Then, the device access timing generation module converts the interpreted patterns into repeat trees for respective pins based on information (for example, timing information) contained in the device access timing generation module about the respective pins. The information can be stored in advance, or can be provided externally based on characteristics of the pins of a Device Under Test (DUT).
In a typical MTL compiler, the semantic processor performs semantic interpretation by expanding a variable to an expression. Through the semantic processor, each assignment is propagated to expressions that reference the assigned variable. Thus, the last expression depends only on loop variables and can be easily evaluated. Each recursive variable is represented by a special expression that calculates the value recursively.
The MTL compiler assumes that the programming patterns of the test program are almost stateless (e.g., there is no historical record or historical state) so that each device access line can be converted into a repeat tree independently. Compression can be performed during merging of the repeat trees generated from multiple device access timing generation modules for one pin. If there is a recursive variable in the test program, for example, a=a+3, it can be optimized by the semantic processor to a=ainit+3*I, wherein “ainit” represents an initial value of the variable a, and “I” represents an index of recursion times. In this example, the expression a=a+3 for the recursive variable a is stateful (e.g., there is a historical record or historical state) programming pattern, and thus calculation of the variable a relies on the historical state of a. By converting the expression of the recursive variable “a” into a=ainit+3*I, the converted expression becomes stateless. At this time, the value of a can be calculated based only on the initial value ainit and the recursion time I, without relying on any historical value of a.
However, if a recursive variable cannot be converted into a stateless expression, it will be calculated recursively, which is very slow.
In addition, as the conventional solution for a per-pin MTL compiler needs to expand the variable to a corresponding expression using a semantic processor. However, scalability is unfortunately limited. When test patterns (programming patterns of a test program) become more complex, the compiling time and memory (internal memory) consumption increase sharply.
For example, when using a PRBS (Pseudo Random Binary Sequence) to test a DDR4 SDRAM (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory), it may be impossible for a conventional MTL compiler to accomplish compilation of DDR4 PRBS test patterns because the PRBS test pattern has complex recursive variables and complex logic and the compilation may require more than 100 G free memory on a workstation.
In test of SoC chip, the logic in the test patterns becomes more and more complex, and registers are simulated in patterns, which are very different from traditional stateless memory test patterns. That is, the patterns used to simulate registers are stateful. In this case, compiling the test patterns consumes substantial memory (several Giga Bytes, for example) on a workstation, and the compiling time is long, for example, more than 1 hour.